Modern wireless transmitters (e.g. for cellular communication, Bluetooth or Wi-Fi) are dominated by two architectures: Cartesian (I/Q) transmitters and polar transmitters.
A digital Cartesian transmitter uses a Radio Frequency Digital-to-Analog Converter (RF-DAC) to generate a modulated radio frequency (RF) signal directly from a complex valued symbol having an in-phase component and a quadrature component. Two Local Oscillator (LO) signals of a same frequency, shifted by 90°, are used to clock the RF-DAC. The LO signals represent the in-phase and quadrature axes (vectors) of the constellation diagram. Cartesian architecture may handle modulation schemes with high bandwidth, but suffers from 3 dB efficiency loss for the worst case symbol (i.e. in-phase and quadrature magnitude of the symbol are equal).
A digital polar transmitter may be attractive for modern radios due to improved area and power consumption compared to conventional analog architectures. In polar architecture, a symbol is expressed by phase and amplitude information. A Digital-to-Time Converter (DTC) may be used to apply phase modulation and/or frequency shifts on a constant LO signal. The modulated output of the DTC may be used to clock a RF-DAC. The RF-DAC may apply amplitude modulation and adjust an output power of the RF signal. One advantage of polar architecture may be a high efficiency of the output stage and that only a single Phase-Locked-Loop (PLL) may provide the LO signal for multiple transmitters. Hence, a number of on-chip inductors may be reduced significantly. However, handling RF signals with a wide bandwidth is problematic with polar architecture.
Hence, there may be a desire for an improved transmitter architecture.